69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
// The I/O APIC manages hardware interrupts for an SMP system.
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// http://www.intel.com/design/chipsets/datashts/29056601.pdf
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// See also picirq.c.
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#include "types.h"
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#include "defs.h"
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#include "traps.h"
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#define IOAPIC 0xFEC00000 // Default physical address of IO APIC
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#define REG_ID 0x00 // Register index: ID
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#define REG_VER 0x01 // Register index: version
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#define REG_TABLE 0x10 // Redirection table base
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// The redirection table starts at REG_TABLE and uses
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// two registers to configure each interrupt.
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// The first (low) register in a pair contains configuration bits.
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// The second (high) register contains a bitmask telling which
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// CPUs can serve that interrupt.
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#define INT_DISABLED 0x00010000 // Interrupt disabled
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#define INT_LEVEL 0x00008000 // Level-triggered (vs edge-)
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#define INT_ACTIVELOW 0x00002000 // Active low (vs high)
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#define INT_LOGICAL 0x00000800 // Destination is CPU id (vs APIC ID)
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volatile struct ioapic *ioapic;
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// IO APIC MMIO structure: write reg, then read or write data.
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struct ioapic {
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uint reg;
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uint pad[3];
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uint data;
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};
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static uint ioapicread(int reg) {
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ioapic->reg = reg;
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return ioapic->data;
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}
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static void ioapicwrite(int reg, uint data) {
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ioapic->reg = reg;
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ioapic->data = data;
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}
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void ioapicinit(void) {
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int i, id, maxintr;
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ioapic = (volatile struct ioapic*)IOAPIC;
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maxintr = (ioapicread(REG_VER) >> 16) & 0xFF;
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id = ioapicread(REG_ID) >> 24;
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if (id != ioapicid) {
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cprintf("ioapicinit: id isn't equal to ioapicid; not a MP\n");
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}
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// Mark all interrupts edge-triggered, active high, disabled,
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// and not routed to any CPUs.
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for (i = 0; i <= maxintr; i++) {
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ioapicwrite(REG_TABLE + 2 * i, INT_DISABLED | (T_IRQ0 + i));
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ioapicwrite(REG_TABLE + 2 * i + 1, 0);
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}
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}
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void ioapicenable(int irq, int cpunum) {
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// Mark interrupt edge-triggered, active high,
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// enabled, and routed to the given cpunum,
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// which happens to be that cpu's APIC ID.
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ioapicwrite(REG_TABLE + 2 * irq, T_IRQ0 + irq);
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ioapicwrite(REG_TABLE + 2 * irq + 1, cpunum << 24);
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}
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